module MyDFF8bit_withAsy (
    input         clk,
    input         rst,         // active-high async load
    input  [7:0]  D,
    input  [7:0]  AsyncVal,    // ResetVal bus
    output [7:0]  Q
);
    genvar i;
    generate
        for (i = 0; i < 8; i = i + 1) begin : dff_bits
            MyDFF1bit_asyncLoad dff (
                .clk(clk),
                .rst(rst),
                .D(D[i]),
                .AsyncVal(AsyncVal[i]),
                .Q_out(Q[i])
            );
        end
    endgenerate
endmodule


module MyDFF1bit_asyncLoad (
    input clk,
    input rst,            // active-high async load
    input D,              // data for sync path
    input AsyncVal,       // parallel value to load on rst
    output Q_out
);
    wire Q1, Q2;
    wire nclk;

    not(nclk, clk);  // inverse clock for master latch

    // master latch: if rst=1, load AsyncVal immediately to Q1
    Register reg_master (
        .clk(nclk),
        .rst_n(~rst),       // active-low reset for master latch
        .D(D),
        .Q(Q1)
    );

    // slave latch: if rst=1, retain previous value in Q2, else use Q1
    Register reg_slave (
        .clk(clk),
        .rst_n(1'b1),       // slave latch is unaffected by rst (should not reset here)
        .D(Q1),
        .Q(Q2)
    );

    // Output: load AsyncVal when rst=1, otherwise use the value from the slave latch
    assign Q_out = rst ? AsyncVal : Q2;
endmodule

